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cy2xf33 high-performance lvds oscillator with frequency margining ? pin control cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 001-53148 rev. *e revised june 13, 2011 features low jitter crystal oscillator (xo) less than 1 ps typical rms phase jitter differential lvds output output frequency from 50 mhz to 690 mhz two frequency margining control pins (fs0, fs1) factory configured or field programmable integrated phase-locked loop (pll) supply voltage: 3.3 v or 2.5 v pb-free package: 5.0 3.2 mm lcc commercial and industrial temperature ranges functional description the cy2xf33 is a high-performance and high-frequency crystal oscillator (xo). it uses a cypress proprietary low-noise pll to synthesize the frequency from an in tegrated crystal. the output frequency can be changed through two select pins, allowing easy frequency margin testing in applications. the cy2xf33 is available as a fa ctory configured device or as a field programmable device. pinouts figure 1. pin diagra m ? 6-pin ceramic lcc logic block diagram output divider 1 fs1 crystal oscillator low-noise pll 4 clk 5 clk# 2 fs0 frequency select decode 1 3 fs1 vss vdd clk 6 4 2 5clk# fs0 table 1. pin definiti ons ? 6-pin ceramic lcc pin name i/o type description 1, 2 fs1, fs0 cmos input frequency select 4, 5 clk, clk# lvds output differential output clock 6 vdd power supply voltage: 2.5 v or 3.3 v 3 vss power ground
cy2xf33 document number: 001-53148 rev. *e page 2 of 12 contents pinouts .............................................................................. 1 contents ............................................................................ 2 functional description ..................................................... 3 programming description ............................................... 3 field programmable cy2xf33f ................................. 3 factory configured cy2xf33 ..................................... 3 application-specific factory configurations ................ 4 programming variables ................................................... 4 output frequencies .. .............. .............. .............. ......... 4 industrial versus commercial device performance .... 4 phase noise versus jitter pe rformance ..................... 4 absolute maximum conditions ....................................... 5 operating conditions ....................................................... 5 dc electrical characteristics .......................................... 5 ac electrical characteristics ........................................... 6 termination circuits ......................................................... 6 switching waveforms ...................................................... 7 ordering information ........................................................ 8 possible configuration ................................................ 8 ordering code definitions ..... ...................................... 8 package drawings and dimensio ns ............................... 9 .acronyms ....................................................................... 10 document conventions ................................................. 10 units of measures ..................................................... 10 document history page ................................................. 11 sales, solutions, and legal information ...................... 11 worldwide sales and design s upport ......... .............. 11 products .................................................................... 11 psoc solutions ......................................................... 11
cy2xf33 document number: 001-53148 rev. *e page 3 of 12 functional description the fs0 and fs1 pins select between four different output frequencies, as shown in ta b l e 3 . frequency margining is a common application for this feature. one frequency is used for the standard operating mode of the device, while the other frequencies are available for margin testing, either during product development or in system manufacturing test. when changing the output frequency, the frequency transition is not guaranteed to be smooth. there can be frequency excursions beyond the start frequency and the new frequency. glitches and runt pulses are possi ble, and time must be allowed for the pll to relock. programming description the cy2xf33 is a programmable device. before being used in an application, it must be programmed with the output frequencies and other variables described in a later section. two different device types are available, each with its own programming flow. they are described in the following sections.5 field programmable cy2xf33f field programmable devices are shipped unprogrammed and must be programmed before being installed on a printed circuit board (pcb). customers use cy berclocks? online software to specify the device configuration and generate a jedec (extension .jed) programming file. programming of samples and prototype quantities is available using a cypress programmer. third party vendors manufacture programmers for small to large volume applications. cypress?s value added distribution partners also provide programming services. field programmable devices are designated with an ?f? in the part number. they are intended for quick prototyping and inventory reduction. the cy2xf33 is one time programmable (otp). the software is located at cyberclocks(tm) online software . factory configured cy2xf33 for customers wanting ready-to -use devices, the cy2xf33 is available with no field progra mming required. all requests are submitted to the local cypress field application engineer (fae) or sales representative. after the request is processed, the user receives a new part number, samples, and data sheet with the programmed values. this part number is used for additional sample requests and production orders. table 2. frequency select fs1 fs0 output frequency 0 0 frequency 0 0 1 frequency 1 1 0 frequency 2 1 1 frequency 3
cy2xf33 document number: 001-53148 rev. *e page 4 of 12 programming variables output frequencies the cy2xf33 is programmed with up to four independent output frequencies, which are then selected using the fs0 and fs1 pins. the device can synthesize frequencies to a resolution of 1 part per million (ppm), but the actual accuracy of the output frequency is limited by the accuracy of the integrated reference crystal. the cy2xf33 has an output frequency range of 50 mhz to 690 mhz, but the range is not continuous. the cy2xf33 cannot generate frequencies in the ranges of 521 mhz to 529 mhz and 596 mhz to 617 mhz. industrial versus commerc ial device performance industrial and commercial devices have different internal crystals. this has a potentially significant impact on performance levels for applications requiring the lowest possible phase noise. cyberclocks online software di splays expected performance for both options. phase noise versus jitter performance in most cases, the device configuration for optimal phase noise performance is different from the device configuration for optimal cycle to cycle or period jitter . cyberclocks online software includes algorithms to optimize performance for either parameter. application-specific factory configurations part number vdd fs1 fs0 output frequency rms phase jitter (random) offset range jitter (typical) cy2xf33lxc700t 3.3 v 0 0 100.00 mhz 12 khz to 20 mhz 0.65 ps 0 1 125.00 mhz 0.61 ps 1 0 200.00 mhz 0.55 ps 1 1 250.00 mhz 0.53 ps table 3. device programming variables variable output frequency 0 (power on default) output frequency 1 output frequency 2 output frequency 3 optimization (phase noise or jitter) temperature range (commercial or industrial)
cy2xf33 document number: 001-53148 rev. *e page 5 of 12 absolute maximum conditions parameter description condition min max unit v dd supply voltage ? ?0.5 4.4 v v in [1] input voltage, dc relative to v ss ?0.5 v dd + 0.5 v t s temperature, storag e non operating ?55 135 ? c t j temperature, junction ? ?40 135 ? c esd hbm esd protection (human body model) jedec std 22-a114-b 2000 ? v ? ja [2] thermal resistance, junction to ambient 0 m/s airflow 64 ? c/w operating conditions parameter description min typ max unit v dd 3.3 v supply voltage range 3.135 3.3 3.465 v 2.5 v supply voltage range 2.375 2.5 2.625 v t pu power up time for v dd to reach minimum specified voltage (power ramp is monotonic) 0.05 ? 500 ms t a ambient temperature (commercial) 0 ? 70 ? c ambient temperature (industrial) ?40 ? 85 ? c notes 1. the voltage on any input or i/o pin cannot exceed the power pin during power up. 2. simulated. the board is derived from the jedec multilayer stand ard. it measures 76 x 114 x 1.6 mm and has 4-layers of copper (2/1/1/2 oz.). the internal layers are 100% copper planes, while the top and bottom layers hav e 50% metalization. no vias are included in the model. 3. i dd includes ~4 ma of current that is dissipated externally in the output termination resistors. 4. not 100% tested, guaranteed by design and characterization. dc electrical characteristics parameter description condition min typ max unit i dd [3] operating supply current v dd = 3.465 v, clk = 150 mhz, output terminated ??120ma v dd = 2.625 v, clk = 150 mhz, output terminated ??115ma v od lvds differential output voltage v dd = 3.3 v or 2.5 v, defined in figure 3 as terminated in figure 2 247?454mv ? v od change in v od between complementary output states v dd = 3.3 v or 2.5 v, defined in figure 3 as terminated in figure 2 ??50mv v os lvds offset output voltage v dd = 3.3 v or 2.5 v, defined in figure 4 as terminated in figure 2 1.125 ? 1.375 v ? v os change in v os between complementary output states v dd = 3.3 v or 2.5 v, r term = 100 ? between clk and clk# ??50mv v ih input high voltage ? 0.7 v dd ?? v v il input low voltage ? ? ? 0.3 v dd v i ih0 input high current, fs0 pin input = v dd ??115 ? a i ih1 input high current, fs1 pin input = v dd ??10 ? a i il0 input low current, fs0 pin input = v ss ?50 ? ? ? a i il1 input low current, fs1 pin input = v ss ?20 ? ? ? a c in0 [4] input capacitance, fs0 pin ? ? 15 ? pf c in1 [4] input capacitance, fs1 pin ? ? 4 ? pf
cy2xf33 document number: 001-53148 rev. *e page 6 of 12 termination circuits figure 2. lvds termination ac electrical characteristics [5] parameter description condition min typ max unit f out output frequency [6] ?50?690mhz fsc frequency stability, commercial devices [7] t a = 0 c to 70 c ? ? 35 ppm fsi frequency stability, industrial devices [7] t a = ?40 c to 85 c ? ? 55 ppm ag aging, 10 years ? ? ? 15 ppm t dc output duty cycle f ?? 450 mhz, measured at zero crossing 45 50 55 % f > 450 mhz, measured at zero crossing 40 50 60 % t r , t f output rise and fall time 20% and 80% of full output swing ? 0.35 1.0 ns t lock startup time time for clk to reach valid frequency measured from the time v dd = v dd (min) ??5 ms t lfs re-lock time time for clk to reach valid frequency from fs0 or fs1 pin change ??1 ms t jitter( ? ) rms phase jitter (random) f out = 106.25 mhz (12 khz?20 mhz) ? 1 ? ps notes 5. not 100% tested, guaranteed by design and characterization. 6. this parameter is specified in cyberclocks online software. 7. frequency stability is the maximum variation in frequency from f 0 . it includes initial accuracy, plus variation from temperature and supply voltage. clk clk# 100 ?
cy2xf33 document number: 001-53148 rev. *e page 7 of 12 switching waveforms figure 3. output voltage swing figure 4. output offset voltage figure 5. output duty cycle timing figure 6. output rise and fall time figure 7. rms phase jitter clk clk# v od2 v od1 ? v od = v od1 - v od2 clk 50 ? clk# 50 ? v os clk t pw t period t dc = t pw t period clk# 20% 80% t r clk 20% 80% clk# t f phase noise phase noise mark offset frequency f1 f2 rms jitter = area under the masked phase noise plot noise power
cy2xf33 document number: 001-53148 rev. *e page 8 of 12 possible configuration some product offerings are factory programmed customer specific devices with customized part nu mbers.the possible configuration s table shows the available device types, but not complete part nu mbers. contact your local cypress fae of sales representative f or more information. ordering information part number configuration package description product flow pb-free CY2XF33FLXCT field programmable 6-pin ceramic lcc smd ? tape and reel commercial, 0 c to 70 c cy2xf33flxit field programmable 6-pin ceramic lcc smd ? tape and reel industrial, ?40 c to 85 c cy2xf33lxc700t [8] factory-configured 6-pin ceramic lcc smd ? tape and reel commercial, 0 c to 70 c part number [9] configuration package description product flow pb-free cy2xf33lxcxxxt factory configured 6-pin ceramic lc c smd ? tape and reel commercial, 0 c to 70 c cy2xf33lxixxxt factory configured 6-pin ceramic lcc smd ? tape and reel industrial, ?40 c to 85 c ordering code definitions t = tape and reel customer specific code temperature range: c = commercial, i = industrial pb-free package type part identifier family company id : cy = cypress xx cy xxx t l x xxx x notes 8. device configuration details are described in the ?application-specific factory configurations? on page 4. 9. ?xxx? is a factory assigned code that identifies the programming option.for more details, contact your local cypress fae or s ales representative.
cy2xf33 document number: 001-53148 rev. *e page 9 of 12 package drawings and dimensions figure 8. 6-pin 3.2 5.0 mm ceramic lcc lz06a . bottom view top view side view 5.0 3.2 0.50 1.30 max 4 6 1 3 typ. typ. 2.54 typ. 0.64 typ. 1.2 typ. 0.45 ref. 0.10 ref. 0.20 r ref. 0.10 r ref. 2 5 index 0.32 r 1.27 typ. 9 10 7 8 dimensions in mm general tolerance: 0.15mm kyocera dwg ref kd-va6432-a package weight ~ 0.12 grams 001-10044-a
cy2xf33 document number: 001-53148 rev. *e page 10 of 12 acronyms document conventions units of measure acronym description clkout clock output cmos complementary metal oxide semiconductor dpm die pick map eprom erasable programmable read only memory lvds low-voltage differential signaling ntsc national television system committee oe output enable pal phase alternate line pd power-down pll phase-locked loop ppm parts per million ttl transistor-transistor logic symbol unit of measure c degrees celsius khz kilohertz k ? kilohm mhz megahertz m ? megaohm a microampere s microsecond v microvolt vrms microvolts root-mean-square ma milliampere mm millimeter ms millisecond mv millivolt na nanoampere ns nanosecond nv nanovolt ? ohm
cy2xf33 document number: 001-53148 rev. *e page 11 of 12 document history page document title: cy2xf33 high-performance lvds oscillator with frequency margining ? pin control document number: 001-53148 revision ecn orig. of change submission date description of change ** 2704379 kvm/pyrs 05/11/2009 new data sheet *a 2734005 wwz 07/09/2009 post to external web *b 2764787 kvm 09/18/2009 change v od limits from 250/450 mv to 247/454 mv add max limit for t r , t f : 1.0 ns change t lock max from 10 ms to 5 ms change t lfs max from 10 ms to 1 ms *c 2898472 kvm 03/24/2010 moved ?xxx? parts to possible configurations table. updated package diagram. *d 3165931 bash 02/10/2011 removed ?preliminary? tag from the document. added ?application specific fact ory configurations? section. added application specific part numbers and note in ordering code information. *e 3279652 bash 06/13/2011 swapped fs0 and fs1 in logic block diagram, pinouts and pin definition on page 1. removed cy2xf33lxc533t from ?application specific factory configurations? and ?ordering information table.?
document number: 001-53148 rev. *e revised june 13, 2011 page 12 of 12 cyberclocks is a trademark of cypress semico nductor corporation. all other products and company names mentioned in this documen t may be the trademarks of their respective holders. cy2xf33 ? cypress semiconductor corporation, 2009-2011. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory optical & image sensing cypress.com/go/image psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5

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